This invention relates generally to test circuits for semiconductor devices, such as memory devices, for example. More particularly, the invention relates to methods and apparatus for evaluating on-chip signals using an on-chip test circuit with an externally applied test signal.
Integrated circuit advances have been rapid in recent years. With each performance advance, testing of integrated circuits has grown more complex. Originally, semiconductor chips were tested with external testers where large complicated test equipment was employed off-chip to evaluate whether the semiconductor's on-chip operation was indeed correct. As semiconductor circuit complexity increased, the capability of external testers was insufficient to the task of testing all circuit functions. Thus followed the development of self-test circuits which aid the external testers in evaluating the proper operation of the on-chip circuitry. These self-test circuits were incorporated on-chip and were used to evaluate the other on-chip circuits which heretofore were not testable by external equipment or at least only with difficulty. Eventually, whole families of built-in self test (BIST) circuits were designed to allow more and more of the test function to be incorporated onto the chip, thereby allowing the external testers to be simpler in nature. Even though the external testers were simpler in nature, due to the addition of on-chip test circuits, the quality of tests and thus the quality of the final chips improved.
Prominent in their ability to be tested by such BIST circuits are semiconductor memory circuits. This includes either stand alone memories such as a memory on a chip whose function was to be a memory, or a memory embedded on a microprocessor or other semiconductor device, such as a chip circuit whose intended function was to be a microprocessor or some other logic function, yet had one or more memories on the chip to enhance the performance and operation of the logic. An example of a BIST circuit for semiconductor memory devices is given in U.S. Pat. No. 5,535,164 issued on Jul. 9, 1996 to Adams et al., entitled "BIST TESTER FOR MULTIPLE MEMORIES," the entire disclosure of which is fully incorporated herein by reference.
With improved memory design came an improvement of memory performance and thus a decrease in memory access and cycle times. The decreases in such times triggered the use of even more aggressive techniques to further improve device performance. Analog circuit techniques were a significant part of the methods used to improve performance. Analog circuits operate differently from digital circuits, the latter being of the type wherein signal values are processed as either a "1" or "0". With analog circuits there are an infinite number of values between the corresponding digital "1" and "0" values. For example, a static random access memory sense amplifier receives an analog signal from a memory cell and amplifies the analog signal sampled at a point in time and converts the amplified signal to a digital "1" or "0". Standard test techniques previously employed for digital circuits were insufficient to fully test analog circuits and signals.
A problem which memory circuit designers encounter is determining the amplitude of the analog signal feeding the sense amplifier at the time the signal is sampled. Prior attempts to measure such signals typically used external signal probes. As circuit impedance, e.g. capacitance, decreases, however, it becomes significantly more difficult to evaluate on-chip signals using conventional techniques such as external probes. This difficulty arises because the probe impedance can adversely affect the signal being measured. Accordingly, there is a need for a technique to evaluate on-chip signals, such as analog signals, without disturbing the signal being evaluated.